During the manufacture of a semiconductor memory, such as a synchronous dynamic random access memories ("SDRAMs"), it is necessary to test the memory to ensure it is operating properly. Electronic and computer systems containing semiconductor memories also normally test the memories when power is initially applied to the system. A typical SDRAM includes at least one array of memory cells arranged in rows and columns, and each memory cell must be tested to ensure it is operating properly. In a typical prior art test method, data having a first binary value (e.g., a "1") is written to and read from all memory cells in the arrays, and thereafter data having a second binary value (e.g., a "0") is typically written to and read from the memory cells. A memory cell is determined to be defective when the data written to the memory cell does not equal that read from the memory cell. As understood by one skilled in the art, other test data patterns may be utilized in testing the memory cells, such as an alternating bit pattern 101010 . . . written to the memory cells in each row of the arrays.
In a typical test configuration, an automated tester is coupled to address, data, and control buses of the SDRAM, and develops signals on these buses to perform the desired tests. The tester applies data transfer commands on the control bus, addresses on the address bus, and either provides or receives data on the data bus depending on whether the data transfer command is a read or write. In addition, the tester develops a clock signal which drives circuitry in the SDRAM to synchronously perform each of the steps involved in a particular data transfer operation as understood by one skilled in the art. The signals developed by the tester must satisfy particular timing parameters of the SDRAM that are typically established relative to particular edges of the clock signal.
In modern SDRAMs, the tester may need to develop a clock signal having a frequency of 100 megahertz or greater, and must also develop the associated address, data, and control signals at increasingly faster rates due to the shorter interval between particular edges of the clock signal. It is known in electronics that as the frequency of operation increases, the circuitry associated with a particular application typically becomes more complex and, as a result, typically more expensive. This is due in part to the potential for coupling electromagnetic energy at high frequencies between circuit lines, the critical nature of physical line lengths at high frequencies, and the potential for small delays to result in inoperability of the circuit. The tester could supply a lower frequency clock signal to the SDRAM, but this would increase the time and thus the cost of testing the SDRAM. Thus, the tester must supply very high frequency clock signals to modern SDRAMs. Testers capable of operating at these higher frequencies typically are more expensive than lower speed testers. In fact, the cost of such testers typically increases exponentially with increases in the frequency of operation. For example, a test operating at 50 megahertz may cost approximately $1 million while a tester operating at 100 megahertz can cost up to $5 million.
In an attempt to minimize the cost of the required tester, many SDRAMs include on-chip test circuitry. In such an SDRAM, the tester develops signals which place the SDRAM in a test mode, and the on-chip test circuitry then writes data to and reads data from the memory cells to verify their proper operation. The results of the tests performed by the on-chip test circuitry are typically provided on a pin or pins of the SDRAM, and the tester then monitors these pins to determine whether the SDRAM is defective. Such on-chip test circuitry is typically able to transfer data to and from the memory cells very quickly reducing the time required for testing the SDRAM. However, the tester must still apply the high frequency clock signal to the SDRAM in order to drive the on-chip test circuitry during testing. In addition, the on-chip test circuitry typically utilizes only a limited number of predetermined test data patterns in testing the memory cells in order to minimize the size and complexity of the on-chip test circuitry. Although the foregoing discussion was directed toward SDRAMs, one skilled in the art will realize such problems exist when testing any high-speed memory device, including SLDRAM, SRAM, and RAMBUS devices, as understood by one skilled in the art.
There is a need for an on-chip test circuit enabling a low frequency tester to test the memory cells in a high-speed memory device with a variety of test data patterns at the desired frequency of operation of the memory device.